• Home
  • Codasip launches the SecuRISC5 initiative
1684268085 Codasip launches the SecuRISC5 initiative | x-3-x

Codasip launches the SecuRISC5 initiative

New approach to safe and secure custom computing

RISC-V Summit, San Jose, December 12, 2022 – Codasip, a leader in processor design automation and RISC-V processor IP, today launched SecuRISC5, a Codasip initiative to provide its customers with safe and secure custom computing using highly verified reference designs that combine the Codasip’s IP and third party technology. Codasip laboratories, recently launched of Codasip, will play a central role in identifying opportunities where SecuRISC5 should focus its attention and will also act as a hub, coordinating pan-industry collaboration.

SecuRISC5 security initiative

Following the recent acquisition of Cerberus Security LabsCodasip is accelerating security developments for its RISC-V processor IP and plans to release security reference designs in 2023. Since a truly secure system cannot be developed in isolation, Codasip is working with partners to provide a complete and secure RISC-V ecosystem.

Jamie Broome, Vice President of Automotive and Products, Codasip, commented: “Safety is the ‘feature’ that people often fail to see the value in, but everyone knows they need. Another important aspect is that without security there is no security and therefore we are taking a holistic approach. We will help our customers integrate RISC-V security and protection by providing more than secure cores. »

“It’s great to see Codasip taking the lead in increasing the security of RISC-V devices; if security is not addressed properly, it poses a potential threat to the wider adoption of RISC-V. We will work closely with Codasip and other ecosystem partners to provide developers with the opportunity to build and test their security concepts using Intel® Pathfinder for RISC-V[2] running in a trusted FPGA environment,” said Vijay Krishnan, general manager, RISC-V Ventures at Intel.

John Hartley, Chief Commercial Officer at Crypto Quantique, said: “Crypto Quantique and Codasip share a mission to enable seamless end-to-end security for RISC-V. For a device to be completely secure, security must be considered from the outset of a development project. It also needs to be scalable and future-proof to ensure systems are protected against all threats throughout the device lifecycle. The only way to manage this is to work together as an industry to ensure safety by design. We welcome this Codasip initiative”.

RISC-V provides an ideal platform for developing the widest range of systems for all types of applications and secure functions, especially for domain specific projects that struggle to get the custom solution or necessary support from proprietary ISAs. RISC-V is increasingly being implemented in security systems[1] and Codasip is active in RISC-V standards processes. The SecuRISC5 initiative will build on the work of the international RISC-V working groups and implement new standards as they are ratified.

Codasip RISC-V processors are also supported by a secure boot feature from Veridify.

Ron Black, CEO of Codasip, to speak about the fundamental disconnect in safety and security during his spotlight presentation RISC-V Summit in San Jose on December 13, 2022. Technology previews of secure IP features and end-to-end IoT security will be showcased at the Codasip booth.

Editor’s Notes:
[1] Recent examples include the open source RISC-V root-of-trust project Open Titan and the Calitra security architecture, required by Google, Microsoft, AMD, and Nvidia for data center security.

[2] Intel, the Intel logo, and other Intel trademarks are trademarks of Intel Corporation or its affiliates. Other names and brands may be claimed as the property of others. No product or component can be absolutely safe.

About Codasip
Codasip offers state-of-the-art RISC-V processor IP and high-level processor design tools, providing IC designers with all the benefits of RISC-V open ISA, along with the unique ability to customize processor IP. As a founding member of RISC-V International and a long-term provider of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors. Founded in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centers in Europe and sales representatives worldwide. For more information about our products and services, visit www.codasip.com. For more information about RISC-V, visit www.riscv.org.

Contacts with the media
Tora Fridholm
Marketing communication manager
+46 761 619134

David Marden
PR and Global Communications
+44 7968 407739